Some of signal transmission devices which transmit a data signal from a transmission end to a reception end have a construction to transmit a data signal synchronized with a clock signal from the transmission end to the reception end, and to determine whether the data signal is “0” or “1” at the reception end based on the clock signal. Since such signal transmission devices read a data signal at the reception end based on the clock signal, there has been a problem that the data signal cannot be read accurately when noise enters the clock signal to generate jitter.
In addition, in a case of optical communication for performing transmission at high rate and of long distance, the jitter of the clock signal may cause a data transmission error. Thus, it is desired that the jitter of the clock signal be sufficiently small. Therefore, in an optical transceiver module for an optical network, the jitter of the clock signal is eliminated such that the optical transceiver module has a construction provided with a clock converter circuit which is constituted of a phase-locked loop (PLL) circuit utilizing a voltage controlled SAW oscillator (VCSO). Further, the optical transceiver module converts, in the clock converter circuit, a low frequency clock having many jitters into a high frequency clock signal with the jitter reduced, and uses this signal as a reference clock signal for multiplexing plural pieces of transmission data into one piece of transmission data. Incidentally, the clock converter circuit suppresses the occurrence of jitter in the signal output from the VCSO, by connecting a first band pass filter to a PLL feedback loop output terminal of the VCSO, and connecting a second band pass filter to an output terminal of a feedback buffer differential amplifier in the VCSO (refer to Patent Document 1, for example).
Patent Document 1: JP-A-2004-120352